1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a vertical metal oxide silicon field-effect transistor (MOSFET) having a trench structure.
2. Description of the Related Art
Vertical MOSFETs may be classified into a so-called planar type and a so-called trench type. Since low on-resistance characteristic can be easily obtained by its structure of a trench type vertical MOSFET, in which a gate electrode is buried in a trench, practical use is in progress. The structure and manufacturing steps of the vertical MOSFET having such a trench structure are disclosed in, for example, Japanese Published Patent Application No. 2002-359294 and Japanese Published Patent Application No. 11-103052.
Two examples of the structure of the conventional vertical MOSFET are described. In the description below, the symbols −, +, and ++ written after N represent relative concentration levels of contained impurities, and the concentration increases in order of −, +, and ++. In the structure illustrated in FIG. 3A, an N+ buried layer 2 is formed on a P type silicon substrate 1, and a P type silicon layer 3 is further formed on the silicon substrate 1. In the P type silicon layer 3, an N− type drain layer 4 is formed so as to reach the N+ buried layer 2, and further, a P type well layer 5 is formed inside the N− type drain layer 4, the N− type drain layer 4 and the P type well layer 5 being formed by diffusion and the like. Further, at a surface outer perimeter portion of the vertical MOSFET other than a portion where an N++ type drain region 12 is later formed, an insulating film 6 is formed. A trench 7 is formed so as to have a depth from the surface of the P type well layer 5 to reach the N− type drain layer 4 beyond the P type well layer 5. Agate oxide film 8 is formed on the surface of the trench and a gate electrode 9 buries inside of the trench. Further, an N++ type source region 11 is provided at a portion adjacent to the P type well layer 5 and the trench 7. Further, the N++ type drain region 12 is provided at the surface of the N− type drain layer. Meanwhile, in the structure of the second example illustrated in FIG. 3B, the gate electrode 9 is protruded from the trench 7. Further, in order to avoid a channel to be formed at an upper end corner portion of the trench 7, an N type source region 10 is formed under the protruding portion of the gate electrode 9, which is a point different from FIG. 3A.
Here, the operation of the vertical MOSFET is briefly described. Under a state in which a forward bias is applied between the drain region 12 and the source region 11, when a predetermined voltage which is equal to or larger than a threshold value is applied to the gate electrode 9, an N type channel is formed in the P type well layer 5 along the trench 7, and thus a current flows between the source region and the drain region. A vertical channel is formed along the trench 7, and hence compared to the case of the planar type vertical MOSFET, a channel width per unit area can be significantly increased. Accordingly, there is an advantage that an on-resistance can be decreased.
Next, a method of manufacturing the vertical MOSFET is briefly described with reference to the case of FIG. 3A. First, the P type silicon substrate 1 is prepared, and at a portion to be formed as the region of the vertical MOSFET, the N+ buried layer 2 is formed by, for example, ion implantation. Then, the P type silicon layer 3 is formed on the silicon substrate 1 by, for example, epitaxial growth. Next, the N− type drain layer 4 is formed at the portion to be formed as the region of the MOSFET by ion implantation or thermal diffusion, and the P type well layer 5 is formed inside the N− type drain layer 4 by ion implantation or thermal diffusion. Next, at a portion to be formed as the region of the gate electrode, the trench 7, which has a depth reaching the N− type drain layer 4 from the surface of the P type well layer 5, is formed. Then, the gate oxide film 8 is formed inside the trench 7, a polysilicon film is provided to cover the entire surface, and then etch-back is performed, to thereby form the gate electrode 9 burying the trench 7. Then, for example, by photolithography, a portion adjacent to the P type well layer 5 and the trench 7 and a part of the surface of the N− type drain layer are opened, and then ion implantation of N type impurities is performed, to thereby form the N++ type source region 11 and the N++ type drain region 12. Then, the insulating film is deposited on the P type silicon layer 3, contact holes are formed in regions on the source region 11, the drain region 12, and the gate electrode 9, and metal electrodes are formed in the contact holes, to thereby form the main structure of the vertical MOSFET.
Meanwhile, in FIG. 3B, the N type source region 10 is formed before the polysilicon film is provided, and after the polysilicon film is provided to cover the entire surface, photoresist covering regions other than a part where the gate electrode 9 is to be formed is removed by photolithography to perform etching, to thereby form the gate electrode.
In the structure illustrated in FIG. 3A, by providing the polysilicon film to cover the entire surface and then performing etch-back, the gate electrode 9 buried in the trench 7 is formed. However, when the gate electrode 9 is subjected to etch-back to be deeper than the depth of the N++ type source region 11, the upper end of the gate electrode 9 will separate from the lower end of the source region 11, disabling the operation of the vertical MOSFET. Japanese Published Patent Application No. 11-103052 thus proposes a solution for this problem by forming an N++ type source region at the gate upper end portion of the side surface of the trench. However, in this method, fluctuations in etch-back directly cause change in channel length of the MOSFET, and hence there is a fear that manufacturing yield decreases.
Meanwhile, in the structure illustrated in FIG. 3B, there is an advantage that, unlike the former case, no influence is exerted by the fluctuations in the etching process. However, the number of manufacturing steps increases compared to that of the former case, and the element area increases, causing increase in unit price per chip, which leads to a cost problem.